Abstract

Quantum low-density parity-check (qLDPC) codes promise to drastically reduce the overhead of fault-tolerant quantum computing architectures. However, all of the known hardware implementations of these codes require advanced technologies: long-range qubit connectivity, high-weight stabilizers, or multi-layered chip layouts. An alternative approach to reduce the hardware overhead of fault-tolerance relies on bosonic cat qubits where bit-flip errors are exponentially suppressed by design.
In this work, we combine both approaches and propose an architecture based on cat qubits concatenated in classical LDPC codes correcting for phase-flips. Employing such phase-flip LDPC codes provides two major advantages. First, the hardware implementation of the code can be realised with short-range qubit interactions in 2D and low-weight stabilizers, which makes it readily compatible with current superconducting circuit technologies. Second, we demonstrate how to implement a fault-tolerant universal set of logical gates with a second layer of cat qubits while maintaining the local connectivity.